An Ultra-Low Power SAR ADC with C-2C Capacitor Array DAC

In order to reduce the power consumption of electronic devices, an ultra-low power SAR ADC with C-2C capacitor array DAC is presented. Firstly, by using C-2C capacitor and tri-level switching scheme, the proposed capacitor array DAC achieves 99.41% switching energy saving and 87.2% capacitor area reduction, compare to conventional switching scheme. Next, dynamic logic SAR and two-stage fully dynamic comparator are used to decrease the power consumption of SAR ADC. Finally, the proposed SAR ADC is implemented in 180 nm CMOS technology with 1 V supply. The simulation results show that, at sampling rate of 100kS/s, the ADC achieves an SNDR of 61.59dB and ENOB of 9.93bits, consumes 0.188W, resulting in a Figure-of-Merit(FOM) of 1.9 fJ/conversion-step. In conclusion, the ultra-low power SAR ADC proposed in this paper is suitable for application in low power electronic devices.