The Design and Simulation of a Low Complexity SAR ADC

In order to reduce the complexity and power consumption of ADCs, a low-power successive approximation analog-to-digital converter (SAR ADC) is designed based on a low-complexity capacitive array DAC. In this structure, only two reference levels are selected for each capacitor of the capacitor array DAC to reduce the complexity of the logic control circuit and the capacitor driving circuit. The LSB capacitor of the capacitor array DAC is involved in the conversion, so that the required total unit capacitance is smaller than that of the monotonic structure, and reduced by half; The comparators adopt two-stage of dynamic structure, reduce the power consumption; The SAR adopts the structure of the dynamic latch circuit, reduce the power consumption and reduce the code error; The capacitive drive circuit adopts CMOS inverter structure, reduce the quantity of the transistor. The simulation results of SAR ADC circuit show that the SAR ADC consumes 0.45 W at a power supply voltage of 1.0 V and a sampling frequency of 100 kHz, with an ENOB of 9.99 bits and single-step conversion power consumption of 4.4 fJ.