Abstract: In order to speed up the operation of traditional large integer division algorithm, a fast low-power algorithm is proposed for big integer division, which is suitable for hardware implementation, and a hardware circuit for the low-power divider is designed. Two big integers are stored in independent random-access memories and combined with the controller and the state machine to realize high-speed data reading and calculation. The proposed divider has the characteristics of high speed and low power consumption. The circuit can support multiple bit width division and modulus calculation as well as up to 4096-bit dividend and 2048-bit divisor. The proposed divider is evaluated and verified using a 130 nm CMOS process in the aspects of area, power consumption and speed. As the results show, the maximum frequency is 125 MHz, the area of the divider is 0.12 mm² and the power consumption is 10 μw/MHz.